Electronic designs often include a group of circuit component or device instances that may be manipulated (e.g., placed) as a group while maintaining the relative positioning of the circuit component or device instances within the group. For example, electronic designs may incorporate an IP (intellectual property) block or cell that may be placed as a group without having to process (e.g., placement, routing, etc.) the devices inside the group. In addition, modern electronic designs with advanced process nodes may allow only specific arrangements of cell or device instances.
Such specific arrangements may also be better suited for manipulation as a group, rather than manipulating the individual instances separately while bearing the risk of violating the specific arrangement requirement or incurring more computational costs. This manipulation of layout instances as a group has become a challenge in modern electronic designs that involve the use of rows in placement of instances. For example, placement rows in a placement layout or floorplan may allow certain types of circuit components and may have different characteristics, attributes, or configurations (e.g., permissible device type(s), permissible orientation(s), alignment requirement(s), offset requirement(s), spacing, etc.) so that when one row accommodates some of the instances in a group, the neighboring row or rows may not accommodate the remaining instances in the same group. In some cases, some advanced nodes may further impose additional alignment requirements that require the fin grids of a multi-gate device design (e.g., a FinFET or Fin Field Effect Transistor) be aligned with that in a layout area (e.g., a row region), and the polysilicon grid of a circuit component design be aligned with that that in a layout area (e.g., a row region).
Conventional approaches often require the tool (e.g., a layout editor, a placement module, etc.) to descend into the group in order to access the individual instances within the group. Such a descent requires opening and checking out the group as well as individual instances from one or more databases in order to place the group in a placement layout and check each instance to determine its legality with respect to each of a plurality of requirements, constraints, and design rules (collectively requirement for singular or requirements for plural). Checking each individual instance against the plurality of requirements, when compounded with the relative placement requirements among the instances within the group, often requires an iterative approach that incrementally moves the group in a layout area hoping to find a viable legal position to place the group while satisfying the plurality of requirements as well as the relative placement requirements. Such conventional approaches fall short due to the excessive computations involved therein.
To further exacerbate the complexities and hence the excessive consumption of computational resources, certain advance technology nodes (e.g., 14 nm technology nodes or below) may further impose additional requirements that include, for example, specific alignment requirements for devices (e.g., a multi-gate device such as a FinFET or Fin Field Effect Transistor) with respect to corresponding grids. For example, one alignment requirement may require the fin grids within a multi-gate device be aligned with the fin grids set forth in the placement layout or a portion thereof (e.g., a region). Another example of such alignment requirements may require the poly grids within device designs be aligned with the poly grid defined in the placement layout or a portion thereof. These additional specific alignment requirements further exacerbate the complexities of finding legal placement solutions for groups.
Certain advanced technology nodes may further require width rules that permit an interconnect of a certain width be located to other interconnects with a limited number of widths. For example, a width rule may require a 58 nm-wide interconnect be located only to interconnects having width values of 40 nm, 46 nm, 62 nm, and 70 nm and prohibits the 58 nm-wide interconnect from being immediately adjacent to interconnects having width values of 32 nm or smaller. These additional track pattern rules further also exacerbate the complexities of finding legal placement solutions for groups.
Therefore, there is a need for implementing group legal placement for an electronic design to address at least the foregoing issues with conventional approaches.